Session 29 — 2026-03-28c
| Field | Value |
|---|---|
| Date | 2026-03-28 |
| Phase | 03b2 — Boot mode selection |
| Duration | ~2 h |
GCC/CNOC Clock Architecture for SDM660/636
No dedicated GCC_TLMM_AHB_CLK exists. TLMM sits on the CNOC (Config NOC) bus. Three CBCR clocks needed:
| Clock | Register | Address |
|---|---|---|
| GCC_SNOC_CNOC_AHB_CBCR | GCC+0x4018 | 0x00104018 |
| GCC_CNOC_PERIPH_SOUTH_AHB_CBCR | GCC+0x501C | 0x0010501C |
| GCC_CNOC_PERIPH_NORTH_AHB_CBCR | GCC+0x5020 | 0x00105020 |
Source: boot_images/QcomPkg/Sdm660Pkg/Library/ClockTargetLib/ClockHWIO.h. CBCR enable protocol: write bit 0 = 1, poll bit 31 until 0. RMSK = 0x80000005. GCC base itself is safe to access from ABL (cannot be clock-gated by the clocks it manages).
ABL v2.3 Design
- Boot path: reverted to v1.6 equivalent — all hall sensor MMIO removed. Boot path is clean.
oem test-sensor: live GCC CNOC clock enable + TLMM GPIO read. If fastboot hangs, power-cycle recovers (no bootloop risk).- NV attempt counter and watchdog removed — unreliable (NV doesn’t survive resets). Not needed for fastboot-only approach.
Source prepared, not yet built. Device needs PBL 9008 recovery first (still bootlooping on v2.2).